The present invention relates to semiconductor fabrication methods, and more particularly to heterojunction bipolar transistors.
Vertical structure heterojunction bipolar transistors are often used in high-frequency applications such as microwave communication systems. Typically, a heterojunction bipolar transistor is constructed from a stack of semiconductor layers in which one of the layers is etched to form a mesa. Typically, it is the emitter that is constructed on the mesa, which overlies the base and collector layers in a vertical arrangement. The emitter ohmic contact is deposited on the top surface of this mesa. The base ohmic contacts are typically deposited adjacent to the mesa on the base layer. The performance of the device is critically dependent on the relative positioning of the emitter and base ohmic contacts.
One prior art method for providing the required alignment utilizes a self-alignment scheme in which the metal layer in the emitter is used to align the metal layer of the base. In these schemes, the emitter metal layer is deposited on the surface of the emitter layer and the emitter layer is then etched using the emitter metal as a mask. The base metal is subsequently deposited using the emitter metal to align the base metal. These schemes frequently involve fabricating the emitter mesa with a wet-etchant that also undercuts the emitter metal and enables the base metal that is subsequently deposited to be self-aligned to the emitter. In addition, the undercut prevents the base metal from forming a bridge that shorts the base metal to the emitter. Unfortunately, the degree of undercutting of the emitter metal in a wet-etchant process is difficult to control. Since this undercut is critical to the device, such fabrication methods have a low device performance and yield due to poor emitter size control and emitter-base shorts.
The present invention includes a transistor and method for making the same. The transistor is constructed from a collector layer, a base layer, and an emitter layer in a stacked arrangement. An emitter contact is patterned on the emitter layer, and the emitter layer is etched to form a mesa on an etched surface, the mesa having a top surface that includes a portion of the emitter layer and sides joining the top surface with the etched surface. A first protective layer is deposited over the emitter contact and the etched surface, and a second protective layer is deposited over the first protective layer. The first and second protective layers are removed over the portions thereof that overlie the etched surface, leaving a portion of the second protective layer on a portion of the sides of the mesa. The first protective layer is then etched with an etchant that removes the first protective layer faster than the second protective layer thereby undercutting a portion of the first protective layer on the sides of the mesa. A patterned metallic layer is then deposited on the etched surface at a position determined by the remaining portion of the second protective layer. The etched surface may be a portion of the base layer or a portion of the emitter layer depending on the desired transistor geometry. The protective layers are preferably dielectrics.